Power Analysis and Instruction Scheduling for Reduced Di/dt in the Execution Core of High-performance Microprocessors

TOBUREN, MARK CHRISTOPHER. Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors. (Under the direction of Dr. Thomas M. Conte.) Power dissipation is becoming a rst-order design issue in high-performance microprocessors as clock speeds and transistor densities continue to increase. As power dissipation levels rise, the cooling and reliability of high-performance processors becomes a major issue. This implies that signi cant research needs to be done in the area of architectural techniques for reducing power dissipation. One major contributor to a processor's average peak power dissipation is the presence of high di=dt in its execution core. High-energy instructions scheduled together in a single cycle can result in large current spikes during execution. In the presence of heavily weighted regions of code, these current spikes can cause increases in the processor's average peak power dissipation. However, if the compiler produces large enough regions, a certain amount of schedule slack should exist, providing opportunities for scheduling optimizations based on per-cycle energy constraints. This thesis proposes a novel approach to instruction scheduling based on the concept of schedule slack, which builds energy e cient schedules by limiting the energy dissipated in a single cycle. In this manner, a more uniform di=dt curve is generated resulting in a decrease in the execution core's average peak power dissipation. POWER ANALYSIS AND INSTRUCTION SCHEDULING FOR REDUCED di/dt IN THE EXECUTION CORE OF HIGH-PERFORMANCE MICROPROCESSORS